1. Field of the Invention
The present invention relates to an isolated DC-DC converter having DC isolation between the input and output thereof and a circuit arranged to perform switching control of the main switching device.
2. Description of the Related Art
FIG. 1 shows a circuit diagram of an isolated switching power supply apparatus disclosed in International Publication Pamphlet No. 2007/018227. Referring to FIG. 1, terminals +Vin and −Vin are respectively the (+) input terminal and (−) input terminal for a DC input power supply. Terminals +Vout and −Vout are respectively the (+) output terminal and (−) output terminal.
This isolated switching power supply apparatus includes an input smoothing capacitor C1, a main transformer T1 having a primary winding n1 and a secondary winding n2, a first switching device Q1 for switching an input voltage applied to the primary winding n1 of the main transformer T1 from the input DC power supply, a square wave oscillator circuit 1 for generating a square wave signal supplied to the gate of the first switching device Q1, a signal reception/power switch driving circuit 2, a rectification side synchronous rectifier Q2 and a commutation side synchronous rectifier Q3 for synchronously rectifying a voltage induced in the secondary winding n2 of the main transformer T1, a synchronous rectifier driving circuit 3 for driving both rectifiers, an off-timing signal transmission circuit 4, a ramp generator circuit 5, an on-period control circuit 6, a choke coil transformer L1, and an output smoothing capacitor C2.
The isolated switching power supply apparatus also includes a pulse transformer T2 and a diode D5 for transmitting an output signal of the off-timing signal transmission circuit 4 to the signal reception/power switch driving circuit 2 in an isolated state.
The square wave oscillator circuit 1 is a multivibrator including inverters IC2 and IC3, and a CR circuit. The signal reception/power switch driving circuit 2 includes an AND gate IC4, a switching device Q4, a resistor R8, and a diode D9.
The synchronous rectifier driving circuit 3 includes a rectification side synchronous rectifier driving terminal FRD and a commutation side synchronous rectifier driving terminal FLY. The off-timing signal transmission circuit 4 includes an AND gate IC5 and a capacitor C7. An on-period control circuit 6 includes a comparator IC1 and a reference power source Vref.
The ramp generator circuit 5 generates a ramp voltage signal using the choke coil transformer L1 and a CR circuit, and inputs the signal to the comparator IC1 of the on-period control circuit 6.
The switching power supply apparatus shown in FIG. 1 constitutes a resonance reset forward converter, in which an input DC power supplied across +Vin and −Vin is, after being smoothed by the input smoothing capacitor C1, converted into an AC power through switching performed by the first switching device Q1 (primary power switch). This AC power is transmitted from the primary winding n1 to the secondary winding n2 of the main transformer T1, and converted back into a DC power, after being rectified by the rectification side synchronous rectifier Q2 and the commutation side synchronous rectifier Q3, and being smoothed by the choke coil transformer L1 and the output smoothing capacitor C2.
The comparator IC1 of the on-period control circuit 6 compares the output voltage at the (+) input and a divided voltage of the reference power source Vref at the (−) input. A ramp wave generated by the ramp generator circuit 5 is superimposed on the divided voltage of the reference power source Vref at the (−) input and gradually diminishes during the on-period of the first switching device Q1. When the (+) input voltage becomes higher than the (−) input voltage during the on-period due to the gradual decrease in the (−) input, the output voltage level of the IC1 changes from an L level to an H level.
The AND gate IC5 keeps detecting the on-period of the first switching device Q1 through the choke coil transformer L1, and when the output voltage of the IC1 changes from an L level to an H level during the on-period of the first switching device Q1, outputs an off-timing signal via the capacitor C7 and transmits the signal from the secondary winding n2 to the primary winding n1 of the pulse transformer T2. At this time, the diode D5 resets the pulse transformer T2 excited by the transmission of the off-timing signal.
The square wave oscillator circuit 1 outputs a square wave having a maximum on-duty ratio. Since the output of the inverter IC2 has a timing opposite that of the square wave oscillator circuit 1, the output capacitor of the switching device Q4 is charged via the diode D9 and the resistor R8 during the off-period of the square wave oscillator circuit, whereby the drain voltage of the switching device Q4 changes to an H level. The AND gate IC4 becomes an H level when both of the output voltage of the square wave oscillator circuit 1 and the drain voltage of the switching device Q4 become an H level. Hence, when the output voltage of the square wave oscillator circuit changes from an L level to an H level, the output of the AND gate IC4 also changes from an L level to an H level, whereby the first switching device Q1 is turned on.
When an off-timing signal is input to the gate of Q4 via the pulse transformer T2 during an on-period of Q1, Q4 is turned on and the charge stored in the output capacitor is discharged. Thereby the drain voltage of Q4 changes from an H level to an L level, and the output of IC4 also changes from an H level to an L level, and hence the first switching device Q1 is turned off.
On the basis of the above-described operation, the signal reception/power switch driving circuit 2 determines the off timing of the first switching device Q1 in synchronization with the turn-on timing of the square wave oscillator circuit 1, and determines the off timing of the first switching device Q1 in synchronization with the turn-off timing, whereby PWM control is performed and the output voltage of the switching power supply is stabilized. Hence, very fast responsiveness is realized without a phase delay caused by a photocoupler or an error amplifier.
In the known isolated switching power supply apparatus without a photocoupler or an error amplifier shown in FIG. 1, the square wave oscillator circuit 1 includes an inverter, and the signal reception/power switch driving circuit 2 includes an AND gate. Since the maximum rated absolute voltage of general high-speed logic ICs is usually approximately 7 V, the gate driving voltage of the first switching device Q1 is limited to a voltage lower than that voltage. To realize a sufficient gate driving voltage, a MOSFET which can drive the first switching device Q1 at a logic level is required; however, a MOSFET which allows logic-level driving with a withstand drain voltage over 100 V is not easily available. In addition, the gate driving power is not satisfactory for a high-power switching power supply which requires a high input capacity for the first switching device Q1.
For these reasons, the known isolated switching power supply configuration shown in FIG. 1 is not suitable for a high-input-voltage and high-power switching power supply.
A possible solution may be a configuration having a two-stage Darlington connection of FETs in which a high-speed logic gate IC uses an output thereof to drive a low-withstand-voltage FET, which in turn drives a high-withstand-voltage FET. Alternatively, an IC for driving a high-withstand-voltage FET may be used which can raise the logic output of approximately 5 V to an output of approximately 8-10 V.
These configurations, however, disadvantageously result in high cost and require high-power resistors resulting in low circuit efficiency.